The subject invention finds use in a high performance data processing system described in the abovecited Cross-Reference 1, and which functions in accordance with the requirements of IBM System/370 data processing systems as defined by the "System/370 Principles of Operation", Form No. GA22-7000.
There are a number of instruction formats defined for the IBM System/370 data processing systems, and many include one or more 4-bit binary fields each of which identify a particular instruction addressable General Purpose Registers (GPR) out of 16 provided in hardware in a Central Processing Unit (CPU). The GPR's have various uses as defined by a programmer.
The various uses for the GPR's is best represented with reference to a particular System/370 instruction defined as a load instruction. In addition to an 8-bit operation field specifying the load instruction, there are three separate 4-bit fields which identify various GPR's. The instruction also includes a 12-bit field (D2) which is an address displacement value. One of the 4-bit fields (R1) identifies a GPR which is to receive and store data accessed from an addressable main storage device. Another of the 4-bit fields (B2) identifies a GPR which stores a base address value. The third 4-bit field (X2) identifies a GPR which provides an address index value. The particular main storage addressable location to be accessed is determined by adding the D2 address displacement value to the base address value stored in the GPR identified by B2, which is further modified by adding to this value the contents of the GPR identified by X2. When the particular main storage address is accessed, the data is transferred to the GPR identified by the R1 field.
Other program instructions may have the same general format as the above defined load instruction but the data accessed from a particular main storage address may, for example, be added to the contents of a GPR identified by R1, and the result stored back into the GPR identified by R1. As with the load instruction, an address generation step is required in which the contents of GPRs identified by B2 and X2 are added to the address displacement field D2 for the purpose of generating the particular main store address of the data to be added to the contents of the register identified by R1.
Many data processing systems, including the one described in the above identified References require at least three separate phases to the handling of each of sequential program instructions. These phases include: (1) the fetching or accessing of an instruction from storage to an instruction register; (2) the decoding of the operation code with main storage address generation if required; and (3) instruction execution. In some data processing systems, certain of the phases may be overlapped. That is, an instruction fetch and/or decode and address generate phase may be performed simultaneously with the execution of an instruction previously decoded.
Certain data processing systems also include a high speed buffer or cache between the main storage device and the CPU. The high speed cache provides faster access to data recently accessed from the main storage device. In some systems, two CPU cycles might be required to access data from the high speed cache, and substantially more CPU cycles would be required to access data from the main storage device. Cross-Reference 2 discloses an improved technique for accessing data in a cache by effecting an associative search for data in the cache using information combined to form a main storage address instead of combining the information to form the address and then using the address for the search.
In the above-identified Cross-Reference 3, the inventive subject matter concerned hardware logic that must be provided in a high performance data processing system, with some degree of overlap of instruction fetch/decode and instruction execution, to detect a sequence of program instruction execution giving rise to an "address generate interlock". This occurs when an instruction being decoded includes address generation requiring use of the contents of a GPR identified by a B2 field as a base address value, and the GPR identified by the B2 field of the instruction being decoded is the same GPR identified by the R1 field of a previous load instruction. The interlock results when the GPR has not yet received the information from the main storage device in response to the load instruction. The address generation interlock inhibits further instruction decoding and address generation until the previous load instruction has been executed. As recognized from the above discussion concerning high-speed caches and main storage devices, the wait for the data, before decoding can proceed, may involve only two CPU cycles or could involve a substantial number of the CPU cycles.
Multiprogramming techniques, task switching, subroutine branching, and many program loops within a program sequence require frequent need to store the present contents of GPR's in main storage and reload new information into the GPR's for a new program sequence. Each time a new program sequence is initiated in the data processing system, there will be a need for one or more of the GPRs to be loaded with base address information and other addressing information utilized during the program sequence, creating many address generation interlock situations.
If more instruction addressable GPR's were provided, more efficiency could be achieved in shifting between program sequences. To increase the number of instruction addressable registers, prior art techniques would suggest the need to provide additional binary bits in the register addressing fields of all instructions. The many programs already written in accordance with the IBM System/370 instruction format would have to be substantially changed.